Top-down and bottom-up approaches to stable clock synthesis

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2003, Pages 575-578

  McCorquodale, Michael S ^a   Ding, Mei Kim ^a   Brown, Richard E ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYSIS AND SIMULATION; BOTTOM UP APPROACH; FREQUENCY MULTIPLICATION; SHORT TERM STABILITY; STABILITY PERFORMANCE; TOPDOWN; BOTTOM UP; BOTTOM-UP SYNTHESIS;

CLOCKS;

ELECTRONICS INDUSTRY;

EID: 33847746231     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2003.1301850     Document Type: Conference Paper

References (5)

1. K. Kunden, "Modeling and Simulation of Jitter in PLL Frequency Synthesizers," Cadence Design Systems, 2001.
2. M. S. McCorquodale, et al., "Study and Simulation of CMOS LC Oscillator Phase Noise and Jitter," lnternutionul Symposium on Cireuirrund Systems, 2003.
3. B. Razavi, RF Microelectronics, New Jersey: Prentice Hall, 1998.
4. Intel StrongARM SA-I 110 Microprocessor Developer's Manual, Intel Corporation, Oct. 2001.
5. T. A. Roessig, el al., "Surface-Micromachined lMHz Oscillator with Low-Noise Pierce Configuration," Solid-Slate Sensor and Achrotor Workshop, 1998.