Improved sub-10-nm CMOS devices with elevated source/drain extensions by tunneling Si-selective-epitaxial-growth

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 145-148

  Wakabayashi, H ^a   Tatsumi, T ^a   Ikarashi, N ^a   Oshida, M ^b   Kawamoto, H ^c   Ikezawa, N ^c   Ikezawa, T ^b   Yamamoto, T ^a   Hane, M ^a   Mochizuki, Y ^a   Mogami, T ^a  

^a System Devices Research Laboratories   (Japan)

^b NEC CORPORATION   (Japan)

^c RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON TUNNELING; EPITAXIAL GROWTH; MOSFET DEVICES; SILICON;

ELEVATED SOURCE/DRAIN EXTENSIONS (ESDE); PARASITIC RESISTANCE; PLANAR BULK CMOS DEVICES; SIDEWALL FILMS;

CMOS INTEGRATED CIRCUITS;

EID: 33847692348     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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