Architectures for silicon nanoelectronics and beyond

Computer

Volumn 40, Issue 1, 2007, Pages 25-33

  Bahar, R Iris ^a   Hammerstrom, Dan ^b   Harlow, Justin ^c   Joyner Jr , William H ^d   Lau, Clifford ^e   Marculescu, Diana ^f   Orailoglu, Alex ^g   Pedram, Massoud ^h  

^a BROWN UNIVERSITY   (United States)

^b PORTLAND STATE UNIVERSITY   (United States)

^c UNIVERSITY OF SOUTH FLORIDA   (United States)

^d SEMICONDUCTOR RESEARCH CORPORATION   (United States)

^e INSTITUTE FOR DEFENSE ANALYSES   (United States)

^f CARNEGIE MELLON UNIVERSITY   (United States)

^g UNIVERSITY OF CALIFORNIA   (United States)

^h UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

Computer architectures; Nanotechnology; Silicon devices

Indexed keywords

EID: 33847607511     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/MC.2007.7     Document Type: Article

References (2)

1. D.B. Strukov and K.K. Likharev, "Defect-Tolerant Architectures for Nanoelectric Crossbar Memories," J. Nanoscience and Nanotechnology, Jan. 2007, pp. 151-167.
2. J.R. Heath et al., "A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology," Science, 12 June 1998, pp. 1716-1721.