Simplified peripheral circuits for a marginally testable 4K RAM

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 1975-February, Issue , 1975, Pages 102-103

  Foss, Richard ^a   Harland, Robert ^a  

^a Microsystems International Ltd ^*  (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; TIMING CIRCUITS;

BITLINE CAPACITANCE; CELL CAPACITANCE; FAILURE POINTS; MEMORY CIRCUITS; PATTERN SENSITIVITY; PERIPHERAL CIRCUITS; SENSE AMPLIFIER; TRANSISTOR CELLS;

RANDOM ACCESS STORAGE;

EID: 33847493301     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.1975.1155354     Document Type: Conference Paper

References (3)

1. Stein, K.U., and Friedrich, H., "A 1 Mil Single Transistor Memory Cell in n Silicon Gate Technology" Journal of Solid State Circuits, p. 319-323; Oct., 1973.
2. Hoffman, W.K., and Kalter, H.L., "An 8Kb Random Access Memory Chip Using the One-Device FET Cell", Ibid. p. 298- 305.
3. Stein, K.U., Sihling, A., and Doering, E., ''Storage Array and Sense/Refresh Circuit for Single-Transistor Memory Cells, Journal of Solid State Circuits, p. 336-340; Oct., 1972.