Improved Vt and Ioff Characteristics of NMOS Transistors Featuring Ultra-Shallow Junctions Obtained by Plasma Doping (PLAD)

European Solid-State Device Research Conference

Volumn , Issue , 2003, Pages 35-38

  Pouydebasque, A ^a   Muller, M ^a   Boeuf, F ^b   Lenoble, D ^b   Lallemen, F ^b   Grouillet, A ^c   Halimaoui, A ^b   El Farhaue, R ^a   Delille, D ^a   Skotnicki, T ^b  

^a NXP SEMICONDUCTORS   (Netherlands)

^b STMICROELECTRONICS   (France)

^c France Telecom R and D   (France)

Author keywords

[No Author keywords available]

Indexed keywords

NMOS TRANSISTORS; PLASMA DOPING; ULTRA SHALLOW JUNCTION;

EID: 33847410435     PISSN: 19308876     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDERC.2003.1256804     Document Type: Conference Paper

References (8)

1. International Technology Roadmap for Semiconductors, 2001 version.
2. J. M. Ha et al., IEDM Tech. Dig., 1998
3. D. Lenoble et al., VLSI Dig. Tech. Papers, 2000
4. K. Lee et al., VLSI Dig. Tech. Papers, 2001
5. D. Lenoble et al., Proc. IIT, 2002
6. M. Müller et al, Proc. ESSDERC, 2002.
7. T. Skotnicki et al., Proc. USJ, 2003
8. T. Skotnicki and F. Boeuf, Proc. ECS, 2002.