Solder joint integrity of various surface finished build-up flip chip packages by 4-point monotonie bending test

Proceedings of 7th Electronics Packaging Technology Conference, EPTC 2005

Volumn 2, Issue , 2005, Pages 465-470

  Nakamura, Tomoko ^a   Miyamoto, Yoshimasa ^a   Hosoi, Yoshihiro ^a   Newman, Keith ^b  

^a KYOCERA CORPORATION   (Japan)

^b SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; FRACTURE TOUGHNESS; INTERMETALLICS; PRINTED CIRCUIT BOARDS; SOLDERING; SURFACE TREATMENT;

BRITTLE FRACTURE RATE; ELECTROLESS NICKEL IMMERSION GOLD (ENIG); SOLDER OVER COPPER (SOC); SURFACE FINISH;

FLIP CHIP DEVICES;

EID: 33847337483     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. IPC/JEDEC Joint Publication IPC/JEDEC-9702, "Monotonie Bend Characterization of Board-Level Interconnects", June 2004.
2. Nicholas Biunno, "A Root Cause Failure Mechanism for Solder Joint Integrity of Electroless Nickel/Immersion Gold Surface Finishes," Proceedings of IPC Printed Circuits Expo, March 14-18, 1999.
3. D. Goyal, et al., "Failure Mechanism of brittle Solder Joint Fracture in the Presence of Electroless Nickel Immersion Gold (ENIG) Interface," Proceedings of 52nd Electronic Components & Technology Conference, San Diego, California, USA, May 28-31, 2002