A temporal logic for input output symbolic transition systems

Proceedings - Asia-Pacific Software Engineering Conference, APSEC

Volumn 2005, Issue , 2005, Pages 43-50

  Aiguier, Marc ^a   Gaston, Christophe ^b   Le Gall, Pascale ^a   Longuet, Delphine ^a   Touil, Assia ^a  

^a UNIVERSITÉ D EVRY VAL D ESSONNE   (France)

^b DIF   (France)

Author keywords

Adequacy; Input output symbolic transition systems; Refinement; Strong bisimulation; Temporal logic

Indexed keywords

COMMUNICATION SYSTEMS; REQUIREMENTS ENGINEERING; SYNCHRONIZATION;

INPUT OUTPUT SYMBOLIC TRANSITION SYSTEMS; STRONG BISIMULATION; TEMPORAL LOGIC;

FORMAL LOGIC;

EID: 33847275159     PISSN: 15301362     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APSEC.2005.19     Document Type: Conference Paper

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