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Volumn 2005, Issue , 2005, Pages

A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps accuracy in 0.35 μm CMOS

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRIC CLOCKS; JITTER;

EID: 33847273782     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (4)

References (7)
  • 1
    • 33845504391 scopus 로고    scopus 로고
    • A DLL based clock generator for a high speed time-interleaved A/D-converter
    • Riga, Latvia November
    • A. Rantala, D. Gomes Martins and M. Åberg, "A DLL based clock generator for a high speed time-interleaved A/D-converter", in Proc. of IEEE Norchip 2003 Conference, Riga, Latvia November 2003
    • (2003) Proc. of IEEE Norchip 2003 Conference
    • Rantala, A.1    Gomes Martins, D.2    Åberg, M.3
  • 2
    • 0036108540 scopus 로고    scopus 로고
    • A 4 Gsample/s 8b ADC in 0.35 μm CMOS
    • Digest of Technical Papers. ISSCC, IEEE International, 20, pp
    • K. Poulton, R. Neff, A. Muto, L. Wei,A. Burstein, M. Heshami, "A 4 Gsample/s 8b ADC in 0.35 μm CMOS" Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International, Volume: 1, 20, pp. 166-457 vol.1
    • (2002) Solid-State Circuits Conference , vol.1 , pp. 166-457
    • Poulton, K.1    Neff, R.2    Muto, A.3    Wei, L.4    Burstein, A.5    Heshami, M.6
  • 4
    • 0036913528 scopus 로고    scopus 로고
    • R. Farjad-Rad, W. Dally, H.-T. Ng, R. Senthinathan, M.-J.E. Lee, R. Rathi, J. Poulton, A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips, Solid-State Circuits, IEEE Journal of, 37 Issue: 12, Dec 2002 Page(s): 1804 -1812
    • R. Farjad-Rad, W. Dally, H.-T. Ng, R. Senthinathan, M.-J.E. Lee, R. Rathi, J. Poulton, "A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips", Solid-State Circuits, IEEE Journal of, Volume: 37 Issue: 12, Dec 2002 Page(s): 1804 -1812
  • 5
    • 33847304225 scopus 로고    scopus 로고
    • http://www.icst.com/products/datasheets/m650.pdf
  • 6
    • 0003458743 scopus 로고    scopus 로고
    • Low-Phase-Noise-Timing-Jitter Design Techniques for Delay Cell Based VCOs and Frequency Synthesizers
    • Dissertation for the degree of Doctor of Technology, University Of California, Berkeley
    • T. C. Weigandt "Low-Phase-Noise-Timing-Jitter Design Techniques for Delay Cell Based VCOs and Frequency Synthesizers", Dissertation for the degree of Doctor of Technology, University Of California, Berkeley, 1998
    • (1998)
    • Weigandt, T.C.1
  • 7
    • 0004083485 scopus 로고    scopus 로고
    • Low-Noise- Local Oscillator Design Techniques using a DLL-based Frequency Multiplier for Wireless Applications
    • Dissertation for the degree of Doctor of Technology, University Of California, Berkeley
    • G. Chien "Low-Noise- Local Oscillator Design Techniques using a DLL-based Frequency Multiplier for Wireless Applications", Dissertation for the degree of Doctor of Technology, University Of California, Berkeley, 2000
    • (2000)
    • Chien, G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.