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1
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33845504391
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A DLL based clock generator for a high speed time-interleaved A/D-converter
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Riga, Latvia November
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A. Rantala, D. Gomes Martins and M. Åberg, "A DLL based clock generator for a high speed time-interleaved A/D-converter", in Proc. of IEEE Norchip 2003 Conference, Riga, Latvia November 2003
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(2003)
Proc. of IEEE Norchip 2003 Conference
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Rantala, A.1
Gomes Martins, D.2
Åberg, M.3
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2
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0036108540
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A 4 Gsample/s 8b ADC in 0.35 μm CMOS
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Digest of Technical Papers. ISSCC, IEEE International, 20, pp
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K. Poulton, R. Neff, A. Muto, L. Wei,A. Burstein, M. Heshami, "A 4 Gsample/s 8b ADC in 0.35 μm CMOS" Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International, Volume: 1, 20, pp. 166-457 vol.1
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Poulton, K.1
Neff, R.2
Muto, A.3
Wei, L.4
Burstein, A.5
Heshami, M.6
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3
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0037630792
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A 20 GS/s 8b ADC witn a 1MB Memory in 0.18 μm CMOS
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Digest of Technical Papers. ISSCC, IEEE International, pp
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K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. kopley, R. Jewett, J. Pernillo, C. Tan, A Monntijo "A 20 GS/s 8b ADC witn a 1MB Memory in 0.18 μm CMOS", Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International, pp. 318-319
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Poulton, K.1
Neff, R.2
Setterberg, B.3
Wuppermann, B.4
kopley, T.5
Jewett, R.6
Pernillo, J.7
Tan, C.8
Monntijo, A.9
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4
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0036913528
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R. Farjad-Rad, W. Dally, H.-T. Ng, R. Senthinathan, M.-J.E. Lee, R. Rathi, J. Poulton, A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips, Solid-State Circuits, IEEE Journal of, 37 Issue: 12, Dec 2002 Page(s): 1804 -1812
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R. Farjad-Rad, W. Dally, H.-T. Ng, R. Senthinathan, M.-J.E. Lee, R. Rathi, J. Poulton, "A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips", Solid-State Circuits, IEEE Journal of, Volume: 37 Issue: 12, Dec 2002 Page(s): 1804 -1812
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5
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33847304225
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http://www.icst.com/products/datasheets/m650.pdf
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6
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0003458743
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Low-Phase-Noise-Timing-Jitter Design Techniques for Delay Cell Based VCOs and Frequency Synthesizers
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Dissertation for the degree of Doctor of Technology, University Of California, Berkeley
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T. C. Weigandt "Low-Phase-Noise-Timing-Jitter Design Techniques for Delay Cell Based VCOs and Frequency Synthesizers", Dissertation for the degree of Doctor of Technology, University Of California, Berkeley, 1998
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(1998)
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Weigandt, T.C.1
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7
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0004083485
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Low-Noise- Local Oscillator Design Techniques using a DLL-based Frequency Multiplier for Wireless Applications
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Dissertation for the degree of Doctor of Technology, University Of California, Berkeley
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G. Chien "Low-Noise- Local Oscillator Design Techniques using a DLL-based Frequency Multiplier for Wireless Applications", Dissertation for the degree of Doctor of Technology, University Of California, Berkeley, 2000
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(2000)
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Chien, G.1
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