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23rd NORCHIP Conference 2005

Volumn 2005, Issue , 2005, Pages

A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps accuracy in 0.35 μm CMOS

(3) Rantala, Arto a Martins, David Gomes a Åberg, Markka a

a VTT TECHNICAL RESEARCH CENTRE OF FINLAND (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRIC CLOCKS; JITTER;

CLOCK GENERATOR CIRCUITS; CLOCK SIGNALS; CONVERTER FINGERS; DELAY LOCKED LOOP (DLL);

ELECTRIC GENERATORS;

EID: 33847273782 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (4)

References (7)

1
- 33845504391
- A DLL based clock generator for a high speed time-interleaved A/D-converter
- Riga, Latvia November
- A. Rantala, D. Gomes Martins and M. Åberg, "A DLL based clock generator for a high speed time-interleaved A/D-converter", in Proc. of IEEE Norchip 2003 Conference, Riga, Latvia November 2003
- (2003) Proc. of IEEE Norchip 2003 Conference
- Rantala, A.¹ Gomes Martins, D.² Åberg, M.³

2
- 0036108540
- A 4 Gsample/s 8b ADC in 0.35 μm CMOS
- Digest of Technical Papers. ISSCC, IEEE International, 20, pp
- K. Poulton, R. Neff, A. Muto, L. Wei,A. Burstein, M. Heshami, "A 4 Gsample/s 8b ADC in 0.35 μm CMOS" Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International, Volume: 1, 20, pp. 166-457 vol.1
- (2002) Solid-State Circuits Conference , vol.1 , pp. 166-457
- Poulton, K.¹ Neff, R.² Muto, A.³ Wei, L.⁴ Burstein, A.⁵ Heshami, M.⁶

3
- 0037630792
- A 20 GS/s 8b ADC witn a 1MB Memory in 0.18 μm CMOS
- Digest of Technical Papers. ISSCC, IEEE International, pp
- K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. kopley, R. Jewett, J. Pernillo, C. Tan, A Monntijo "A 20 GS/s 8b ADC witn a 1MB Memory in 0.18 μm CMOS", Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International, pp. 318-319
- (2003) Solid-State Circuits Conference , pp. 318-319
- Poulton, K.¹ Neff, R.² Setterberg, B.³ Wuppermann, B.⁴ kopley, T.⁵ Jewett, R.⁶ Pernillo, J.⁷ Tan, C.⁸ Monntijo, A.⁹

4
- 0036913528
- R. Farjad-Rad, W. Dally, H.-T. Ng, R. Senthinathan, M.-J.E. Lee, R. Rathi, J. Poulton, A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips, Solid-State Circuits, IEEE Journal of, 37 Issue: 12, Dec 2002 Page(s): 1804 -1812
- R. Farjad-Rad, W. Dally, H.-T. Ng, R. Senthinathan, M.-J.E. Lee, R. Rathi, J. Poulton, "A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips", Solid-State Circuits, IEEE Journal of, Volume: 37 Issue: 12, Dec 2002 Page(s): 1804 -1812

5
- 33847304225
- http://www.icst.com/products/datasheets/m650.pdf

6
- 0003458743
- Low-Phase-Noise-Timing-Jitter Design Techniques for Delay Cell Based VCOs and Frequency Synthesizers
- Dissertation for the degree of Doctor of Technology, University Of California, Berkeley
- T. C. Weigandt "Low-Phase-Noise-Timing-Jitter Design Techniques for Delay Cell Based VCOs and Frequency Synthesizers", Dissertation for the degree of Doctor of Technology, University Of California, Berkeley, 1998
- (1998)
- Weigandt, T.C.¹

7
- 0004083485
- Low-Noise- Local Oscillator Design Techniques using a DLL-based Frequency Multiplier for Wireless Applications
- Dissertation for the degree of Doctor of Technology, University Of California, Berkeley
- G. Chien "Low-Noise- Local Oscillator Design Techniques using a DLL-based Frequency Multiplier for Wireless Applications", Dissertation for the degree of Doctor of Technology, University Of California, Berkeley, 2000
- (2000)
- Chien, G.¹

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.