Hardware-efficient computing architecture for motion compensation interpolation in H.264 video coding

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 2136-2139

  Lie, Wen Nung ^a   Yeh, Han Ching ^a   Lin, Tom C I ^a   Chen, Chien Fa ^b  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTING ARCHITECTURE; H.264 STANDARDS; H.264 VIDEO CODECS; H.264 VIDEO CODING; HARDWARE IMPLEMENTATIONS; LINEAR FILTERS; PSNR PERFORMANCE; QUALITY DEGRADATION; QUARTER-PIXEL; RECURSIVE ALGORITHMS;

FIR FILTERS; HARDWARE; IMAGE CODING; MOTION COMPENSATION; VISUAL COMMUNICATION;

INTERPOLATION;

EID: 33847240264     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465042     Document Type: Conference Paper

References (4)

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2. M. Horowitz, A. Joch, F. Kossentini, and A. Hallapuro, "H.264/AVC baseline profile decoder complexity analysis," IEEE Tran. Circ. Sys. Video Tech., vol. 13, no 7, pp. 715-727, 2003.
3. J. Lee, S. Moon and W. Sung, "H.264 Decoder Optimization Exploiting SIMD Instructions," Accepted by IEEE Asia-Pacific Conference on Circuits and Systems, (APCCAS), Dec. 2004
4. K. Sato, Y. Yagasaki, "Adaptive MC interpolation for memory access reduction in JVT video coding ," Proc. Of Seventh Int. Sym. on Signal Processing and Its Applications, Vol.1, July 2003.