Implementing non power-of-two FFTs on coarse-grain reconfigurable architectures

2005 International Symposium on System-on-Chip, Proceedings

Volumn 2005, Issue , 2005, Pages 74-77

  Rivaton, Arnaud ^a   Quévremont, Jérôme ^a   Zhang, Qiwei ^b   Wolkotte, Pascal ^b   Smit, Gerard ^b  

^a THALES COMMUNICATIONS   (France)

^b UNIVERSITY OF TWENTE   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BROADCASTING; ENERGY DISSIPATION; FAST FOURIER TRANSFORMS; REDUCED INSTRUCTION SET COMPUTING; RESOURCE ALLOCATION;

COARSE GRAIN ARCHITECTURE; PROCESSING TIME; RESOURCE UTILIZATION;

COMPUTER ARCHITECTURE;

EID: 33847202228     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/issoc.2005.1595648     Document Type: Conference Paper

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