Distributed arithmetic in the design of high speed hardware fuzzy inference systems

Annual Conference of the North American Fuzzy Information Processing Society - NAFIPS

Volumn 2003-January, Issue , 2003, Pages 116-120

  Gaona, A ^a   Olea, D ^a   Melgarejo, M ^a  

^a UNIVERSIDAD DISTRITAL FRANCISCO JOSÉ DE CALDAS   (Colombia)

Author keywords

Arithmetic; Automation; Computer architecture; Engines; Field programmable gate arrays; Fuzzy sets; Fuzzy systems; Hardware; Laboratories; Microelectronics

Indexed keywords

AUTOMATIC PROGRAMMING; AUTOMATION; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DIGITAL ARITHMETIC; ENGINES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FILTER BANKS; FUZZY SETS; FUZZY SYSTEMS; HARDWARE; INFORMATION SCIENCE; INTEGRATED CIRCUIT DESIGN; LABORATORIES; MICROELECTRONICS; PARALLEL PROCESSING SYSTEMS;

CODE GENERATION TOOLS; DEFUZZIFIERS; DISTRIBUTED ARITHMETIC; FUZZY INFERENCE SYSTEMS; FUZZY PROCESSOR; HIGH SPEED; PROCESSING SPEED; SYSTEM LEVELS;

FUZZY INFERENCE;

EID: 33847179841     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NAFIPS.2003.1226766     Document Type: Conference Paper

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