Securing embedded programmable gate arrays in secure circuits

20th International Parallel and Distributed Processing Symposium, IPDPS 2006

Volumn 2006, Issue , 2006, Pages

  Valette, Nicolas ^a,b   Torres, Lionel ^b   Sassatelli, Gilles ^b   Bancel, Frédéric ^a  

^a STMICROELECTRONICS   (France)

^b LIRMM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; EMBEDDED SYSTEMS; INTERFACES (COMPUTER); SECURITY SYSTEMS;

CONFIGURATION MEMORY PROGRAMMING; EMBEDDED PROGRAMMABLE GATE ARRAYS; INTERFACING ARCHITECTURE; SECURE CIRCUITS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 33847171578     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2006.1639483     Document Type: Conference Paper

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