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Volumn 2005, Issue , 2005, Pages 982-991

A leakage control system for thermal stability during burn-in test

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FEEDBACK; LEAKAGE CURRENTS; THERMODYNAMIC STABILITY;

EID: 33847166551     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TEST.2005.1584064     Document Type: Conference Paper
Times cited : (17)

References (20)
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  • 5
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    • Effect of CMOS Technology Scaling on Thermal Management During Burn-In
    • Nov
    • O. Semenov, et. al, "Effect of CMOS Technology Scaling on Thermal Management During Burn-In", IEEE Trans. on Semiconductor Manufacturing, vol. 16, No. 4, pp. 686-695, Nov, 2003
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    • Semenov, O.1    et., al.2
  • 9
    • 0003285247 scopus 로고    scopus 로고
    • Thermal Challenges During Microprocessor Testing
    • P. Tadayon, "Thermal Challenges During Microprocessor Testing", Intel Tech. Journal Q3, 2000.
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    • Tadayon, P.1
  • 11
    • 0028430427 scopus 로고
    • 2 breakdown model for very low voltage lifetime extrapolation
    • May
    • 2 breakdown model for very low voltage lifetime extrapolation", IEEE Trans. on Electron Devices, vol. 41, pp. 761-767, May 1994.
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    • Schuegraf, K.1    et., al.2
  • 12
    • 0033894378 scopus 로고    scopus 로고
    • A New Model for the Description of Gate Voltage and Temperature Dependence of Gate Induced Drain Leakage (GIDL) in the Low Electric Field Region
    • Jan
    • M. Rosar, et. al, "A New Model for the Description of Gate Voltage and Temperature Dependence of Gate Induced Drain Leakage (GIDL) in the Low Electric Field Region", IEEE Trans. on Electorn Devices, vol. 47, No.1, pp. 154-159, Jan, 2000.
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    • Rosar, M.1    et., al.2
  • 13
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    • Optimal body bias selection for leakage improvement and process compensation over different technology generations
    • C. Neau, et. al, "Optimal body bias selection for leakage improvement and process compensation over different technology generations", Int. Symp. Low Power Electronics and Design (ISLPED), 2003.
    • (2003) Int. Symp. Low Power Electronics and Design (ISLPED)
    • Neau, C.1    et., al.2
  • 14
    • 0037246068 scopus 로고    scopus 로고
    • A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETS
    • Jan
    • G. Giustolisi, et. al, "A Low-Voltage Low-Power Voltage Reference Based on Subthreshold MOSFETS", IEEE Journal of Solid-State Circuits, vol. 38, No. 1, Jan, 2003
    • (2003) IEEE Journal of Solid-State Circuits , vol.38 , Issue.1
    • Giustolisi, G.1    et., al.2
  • 15
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    • dd and temperature independent CMOS voltage reference circuit
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    • dd and temperature independent CMOS voltage reference circuit", Proceedings of ASP-DAC, pp. 559-560, Jan, 2004.
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    • S. Rusu, Trends and challenge in VLSI technology scaling toward 100nm. Presented at ESSCIRC. [Online]. Available: http://www.ess-circ.org/esscirc2001/ C01_Presentations/404.pdf
    • S. Rusu, Trends and challenge in VLSI technology scaling toward 100nm. Presented at ESSCIRC. [Online]. Available: http://www.ess-circ.org/esscirc2001/ C01_Presentations/404.pdf
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.