A GSM receiver front-end in 65nm digital CMOS process

Proceedings of the Custom Integrated Circuits Conference

Volumn 2005, Issue , 2005, Pages 349-352

  Lee, See Taur ^a   Peng, Solti ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

1dB compression point (P1dB); Conversion gain; GSM; I Q demodulator; LNA; Mixer; Noise figure (NF); Second order input intercept point (IIP2); Third order input intercept point (IIP3)

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL DEVICES; GAIN CONTROL; GLOBAL SYSTEM FOR MOBILE COMMUNICATIONS; SPURIOUS SIGNAL NOISE;

1DB COMPRESSION POINT (P1DB); CONVERSION GAIN; I/Q DEMODULATOR; NOISE FIGURE (NF); SECOND ORDER INPUT INTERCEPT POINT (IIP2); THIRD ORDER INPUT INTERCEPT POINT (IIP3);

SIGNAL RECEIVERS;

EID: 33847146337     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2005.1568677     Document Type: Conference Paper

References (3)

1. Ozan E. Erdogan, et al., "A Single-Chip Quad-Band GSM/GPRS Transceiver in 0.18μm Standard CMOS", in ISSCC Dig. Tech. Papers, 2005, pp. 318-319.
2. Leroux, et al., "A 0.8dB NF BSD-protected 9mW CMOS LNA", mISSCC Dig. Tech. Papers, 2001, pp. 410-411.
3. Solti Peng, et al., "A Wide-band Mixer for WCDMA/CDMA2000 in 90nm Digital CMOS Process", IEEE RFIC Symposium, 2005, pp. 179-182.