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Volumn 2005, Issue , 2005, Pages 240-244
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FPGA based implementation of MPEG-2 compression algorithm
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Author keywords
Discrete cosine transform; Hardware architecture; Motion estimation and compensation; MPEG 2 compression; Quantization; SAD operations
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Indexed keywords
ALGORITHMS;
COMPUTATIONAL COMPLEXITY;
COMPUTATIONAL METHODS;
COMPUTER HARDWARE;
COSINE TRANSFORMS;
FIELD PROGRAMMABLE GATE ARRAYS (FPGA);
MOTION COMPENSATION;
MOTION ESTIMATION;
COMPUTATIONAL EFFICIENCY;
DISCRETE COSINE TRANSFORM (DCT);
HARDWARE ARCHITECTURE;
PEAK NOISE TO SIGNAL RATIO (PNSR);
IMAGE COMPRESSION;
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EID: 33847135713
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ICM.2005.1590075 Document Type: Conference Paper |
Times cited : (2)
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References (10)
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