PE-ICE: Parallelized Encryption and Integrity Checking Engine

2006 IEEE Design and Diagnostics of Electronic Circuits and systems

Volumn 2006, Issue , 2006, Pages 141-142

  Elbaz, R ^a   Torres, L ^a   Sassatelli, G ^a   Guillemin, P ^b   Bardouillet, M ^b  

^a CNRS   (France)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CHIP SCALE PACKAGES; CRYPTOGRAPHY; DATA FLOW ANALYSIS; PARALLEL PROCESSING SYSTEMS;

DATA EXCHANGE; ENCRYPTION ALGORITHMS; INTEGRITY CHECKING ENGINE; SYSTEM ON CHIP (SOC);

INFERENCE ENGINES;

EID: 33847127403     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DDECS.2006.1649595     Document Type: Conference Paper

References (5)

1. G. E. Suh, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas, AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing, in Proc. Intl Conf. Supercomputing (ICS '03), pp. 160-171, June 2003.
2. G. E. Suh, D. Clarke, B. Gassend, M. van Dijk, and S. Devadas, Efficient Memory Integrity Verification and Encryption for Secure Processors, 36th IEEE/ACM Intl. Symposium on Microarchitecture, p.339, 2003.
3. M. Bellare and C. Namprempre. Authenticated encryption: Relations among notions and analysis of the generic construction paradigm. In T. Okamoto, editor, Asiacrypt 2000, volume 1976 of LNCS, pages 531-545. Springer-Verlag, Berlin Germany, Dec. 2000.
4. http://csrc.nist.gov/CryptoToolkit/aes/rijndael/
5. S. Segars, The ARM9 Family - High Performance Microprocessors for Embedded Applications, in Proc. Of the IEEE International Conference on Computer design, 1998.