A 16-bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise Shaping

IEEE Journal of Solid-State Circuits

Volumn 22, Issue 6, 1987, Pages 921-929

  Matsuya, Yasuyuki ^a   Uchimura, Kuniharu ^a   Iwata, Atsushi ^a   Kobayashi, Tsutomu ^a   Ishikawa, Masayuki ^a   Yoshitome, Takeshi ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 33847126300     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/JSSC.1987.1052839     Document Type: Article

References (16)

1. R. J. Van DePlassche and H. J. Schouwenaars, “A monolithic 14 bit A/D converter,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 1112–1117, Dec. 1982.
2. J. R. Naylor, “A complete high-speed voltage output 16 bit monolithic DAC,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 729–735, Dec. 1983.
3. Y. Matsuya, Y. Akazawa, and A. Iwata, “High linearity and high speed 1 chip A to D, D to A converter,” Trans. Inst. Electron. Commun. Eng. Japan, vol. J69-C, 531–539, 1986.
4. R. V. Plassche, “Dynamic element matching puts trimless converters on chip,” in Electronics. Boulder, CO: Lake Publ. Corp., June 16, 1983, 130–134.
5. Y. Matsuya, Y. Akazawa, and A. Iwata, “Error analysis of weighting networks,” paper of the Tech. Group on Semiconductors and Semiconductor Devices, IECE (Japan), vol. 81, SSD 81–58, pp. 25–32, Nov. 1981.
6. T. Sugawara, M. Ishibe, H. Yamada, S. Majima, T. Tanji, and S. Komatsu, “A monolithic 14 bit/20 μs dual channel A/D converters,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 723–728, Dec. 1983.
7. B. Agrawal and K. Shenoi, “Design methodology for ∑ΔM,” IEEE Trans. Commun., vol. CE-31, 360–370, Mar. 1983.
8. J. C. Candy, “A use of limit cycle oscillations to obtain robust analog to digital converters,” IEEE Trans. Commun., vol. COM-22, pp. 298–305, Mar. 1974.
9. P. Koch, B. Heise, F. Eckbauer, E. Engelhardt, J. A. Fisher, and F. Parzefall, “A 12 bit sigma-delta analog to digital converter with 15 MHz clock rate,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 1003–1009, Dec. 1986.
10. J. W. Scott, W. Lee, C. H. Giancarlo, and C. G. Sodini, “CMOS implementation of an immediately adaptive delta modulator,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 1088–1095, Dec. 1983.
11. K. Uchimura, T. Hayashi, T. Kimura, and A. Iwata, “VLSI A to D and D to A converters with multi-stage noise shaping modulators,” in Proc. ICASSP, Apr. 1986, pp. 1545–1548.
12. T. Hayashi, Y. Inabe, K. Uchimura, and T. Kimura, “A multi stage delta-sigma modulator without double integration loop,” in ISSCC Dig. Tech. Papers, Feb. 1986, pp. 182–183.
13. S. K. Tewksbury and R. W. Hallock, “Oversampled, linear predictive and noise-shaping coders of order N < 1,” IEEE Trans. Circuits Syst., vol. CAS-25, pp. 436–447, July 1978.
14. J. A. Guinea and D. Senderowicz, “A differential narrow-band switched capacitor filtering technique,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 1029–1038, Dec. 1982.
15. T. Choi, R. T. Kaneshiro, R. W. Brodersen, P. R. Gray, W. B. Jett, and M. Wilcox, “High-frequency CMOS switched-capacitor filters for communications application,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 652–664, Dec. 1983.
16. L. R. Rabiner and B. Gold, Theory and Application of Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, pp. 328–334.