Towards an understanding of no trouble found devices

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2005, Pages 147-152

  Davidson, Scott ^a  

^a SUN MICROSYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIFFERENT STAGES; NO TROUBLE FOUND; PRODUCT LIFE CYCLES;

ELECTRICAL ENGINEERING;

EID: 33847105793     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2005.86     Document Type: Conference Paper

References (7)

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2. V. D. Agrawal, S. C. Seth, and P. Agrawal, "Fault Coverage Requirements in Production Testing of LSI Circuits," IEEE J. Solid State Circuits, Vol. SC-17, No. 1, Feb. 1982, pp. 57-61.
3. P. Maxwell and R. Aitken, "All Fault Coverages are Not Created Equal", IEEE Design & Test of Computers, Mar. 1993, pp. 42-51.
4. Y. Nishizaki, O. Nakayama, C. Matsumoto, Y. Kimura, T. Kobayashi, and H. Nakamura, "Testing DSM ASIC with Static, IDDQ, and Dynamic Test Suite: Implementation and Results," Proc. 2003 International Test Conf., October 2003, pp. 85-94.
5. P. Maxwell, R. Aitken, V. Johansen, and I. Chang, "The Effect of Different Test Sets on Quality Level Prediction: When is 80% Better Than 90%?" Proc. 1991 International Test Conf., October 1991, pp. 358-364.
6. E. J. McCluskey and C. W. Tseng, "Stuck-Fault Tests vs. Actual Defects," Proc. 2000 International Test Conf., October 2000, pp. 336-343.
7. B. Benware, C. Schuermyer, S. Ranganathan, R. Madge, P. Krishnamurthy, N. Tamarapalli, K. Tsai, and J. Rajski, "Impact of Multiple-Detect Test Patterns on Product Quality," Proc. 2003 International Test Conf., October 2003, pp. 1031-1040