VHDL to FPGA automatic IP-Core generation: A case study on Xilinx design flow

20th International Parallel and Distributed Processing Symposium, IPDPS 2006

Volumn 2006, Issue , 2006, Pages

  Ferrandi, Fabrizio ^a   Ferrara, Giovanna ^b   Palazzo, Roberto ^a   Rana, Vincenzo ^a   Santambrogio, Marco D ^a  

^a POLITECNICO DI MILANO   (Italy)

^b Siemens SpA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER AIDED DESIGN; COMPUTER ARCHITECTURE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTERFACES (COMPUTER);

CLASSICAL XILINX DESIGN; COMMUNICATION INFRASTRUCTURE; IP-CORES; VHDL;

NETWORK PROTOCOLS;

EID: 33847095175     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2006.1639491     Document Type: Conference Paper

References (5)

1. Xilinx Inc. Embedded Development Kit EDK 7.1i. Xilinx Inc., 2005.
2. IBM corporation. The CoreConnect Bus Architecture, white paper. International Business Machines Corporation., 2004.
3. IBM Corporation. IBM official website. http://www-03.ibm.com/ chips/products/coreconnect/.
4. Tien-Lung Lee and Neil W. Bergmann. An interface methodology for retargettable fpga peripherals. In Engineering of Reconfigurable Systems and Algorithms, pages 167-173, 2003.
5. Alberto Donato, Fabrizio Ferrandi, Marco D. Santambrogio, and Donatella Sciuto. Exploiting partial dynamic reconfiguration for soc design of complex application on fpga platforms. In IFIP VLSI-SOC 2005, 2005.