A background compensation technique for sample-time errors in time-interleaved A/D converters

Midwest Symposium on Circuits and Systems

Volumn 2005, Issue , 2005, Pages 1011-1014

  Haftbaradaran, Afshin ^a   Martin, Kenneth W ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; COMPUTER SIMULATION; DATA COMMUNICATION SYSTEMS; ERROR ANALYSIS; ERROR COMPENSATION; ERROR CORRECTION;

BACKGROUND COMPENSATION TECHNIQUE; CALIBRATION SIGNAL; DIGITAL DATA COMMUNICATION SYSTEMS; TIME INTERLEAVED A/D CONVERTERS;

ANALOG TO DIGITAL CONVERSION;

EID: 33847093442     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2005.1594275     Document Type: Conference Paper

References (4)

1. W. Black, and D. Hodges, "Time interleaved converter arrays," IEEE J. Solid-State Circuits, vol. SC-15, pp. 1022-1029, Dec. 1980.
2. A. Petraglia, S. K. Mitra, "Analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizer," IEEE Trans. Instrum. Measur., vol. 40, pp. 831-835, Oct. 1991.
3. N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, "Explicit analysis of channel mismatch effects in time-interleaved ADC systems," IEEE Trans. Circuits and Systems-I: Fundamental Theory and Applications, vol. 48, pp. 261-271, Mar. 2001.
4. H. Jin, E. K. F. Lee, "A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADC's," IEEE Trans. Circuits and Systems-II: Analog and Digital Signal Processing, vol. 47, pp. 603-613, Jul. 2000.