A 15 GHz and a 20 GHz low noise amplifier in 90 nm RF-CMOS

2006 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems - Digest of Papers

Volumn 2006, Issue , 2006, Pages 387-390

  Aspemyr, Lars ^a,b   Jacobsson, Harald ^a   Bao, Mingquan ^a   Sjöland, Henrik ^b   Ferndahl, Mattias ^c   Carchon, Geert ^d  

^a Ericsson Microwave Systems AB   (Sweden)

^b LUND UNIVERSITY   (Sweden)

^c CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

^d IMEC   (Belgium)

Author keywords

90 nm; LNA; Low noise amplifier; Noise figure; RF CMOS

Indexed keywords

AUDIO FREQUENCY AMPLIFIERS; ELECTRIC POWER UTILIZATION; PRODUCT DESIGN;

LOW-NOISE AMPLIFIERS; NOISE FIGURE; POWER GAIN;

CMOS INTEGRATED CIRCUITS;

EID: 33847076469     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SMIC.2005.1588004     Document Type: Conference Paper

References (8)

1. G. J. Carchon, W. De Raedt; E. Beyne, "Wafer-level packaging technology for high-Q on-chip inductors and transmission lines", IEEE Transactions on Microwave Theory and Techniques, Volume 52, Issue 4, April 2004, pp. 1244-1251.
2. M. A. Masud, H. Zirath, M. Ferndahl and H.-O. Vickes, "90 nm CMOS MMIC amplifier," IEEE RFIC Symposium, 2004, pp. 201-204.
3. F. Ellinger, "26-42 SOI CMOS Low Noise Amplifier," IEEE Journal of Solid State Circuits, vol. 39, no.3, March 2004, pp. 522-528.
4. K.-W. Yu and M. F. Chang, "CMOS K-Band LNAs design counting both interconnect transmission lines and RF pad parasitics", IEEE RFIC Symposium, pp 101-104, 2004.
5. X. Guan and A. Hajimiri, "A 24-GHz CMOS Front-End," IEEE Journal of Solid-State Circuits, vol. 39, no. 2, February 2004, pp. 368-373.
6. B. A. Floyd et al., "A 23.8-GHz SOI CMOS tuned amplifier," IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 50, September 2002, pp. 2193-2195.
7. S.-C. Shin et al., "A 24-GHz 3.9-dB NF low-noise amplifier using 0.18 μm CMOS technology", IEEE Microwave and Wireless Components Letter, vol. 15, no. 7, July 2005, pp. 448-450.
8. R. Brederlow et al., "A mixed signal design roadmap", IEEE Design & Test of Computers, Vol. 18, No. 6, November-December 2001 pp. 34-36.