Nickel selective etching studies for self-aligned silicide process in Ge and SiGe-based devices

ECS Transactions

Volumn 3, Issue 7, 2006, Pages 643-654

  Carron, V ^a   Ribeiro, M ^a   Besson, P ^b   Rolland, G ^a   Hartmann, J M ^a   Loup, V ^a   Minoret, S ^a   Clavelier, L ^a   Leroyer, C ^a   Billon, T ^a  

^a CEA LETI   (France)

^b STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ETCHING; NICKEL; SILICON ALLOYS; SOLUTIONS;

ETCH RATE; GERMANOSILICIDE LAYER; SELF-ALIGNED SILICIDE; SILICON-GERMANIUM ALLOYS;

SEMICONDUCTOR DEVICES;

EID: 33846989454     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.2355860     Document Type: Conference Paper

References (12)

1. S.-L. Zhang, in Advanced Gate Stack, Source/Drain and Channel Engineering for Si-Based CMOS: New Materials, Processes and Equipment/2005, E. P. Gusev et al. Editors, PV 2005-05, p. 597, The Electrochemical Society Proceedings Series, Pennington, NJ (2005).
2. Rui Li et al., Thin Solid Films, 504, 28 (2006).
3. S. E. Thompson et al., IEEE Electron Device Lett., 25, 191, (2004).
4. Shiyang Zhu et al., IEEE Electron Device Lett., 26, 81, (2006).
5. T. Morimoto et al., IEEE Trans. Electron Dev., 42, 915, (1995).
6. A. Lauwers et al., Microelectron. Eng., 50, 103, (2000).
7. Y. Bogumilowicz et al., J. Cryst. Growth, 290, 523 (2006).
8. 2Si JCPDS file 48-1339.
9. NiSi JCPDS file 38-0844.
10. NiGe JCPDS file 65-1478.
11. J. Seger et al., Appl. Phys. Lett., 81 (11), (2002).
12. T. Jarmar et al., J. Appl. Phys., 92(12), 7193, (2002).