(Self-)reconfigurable finite state machines: Theory and implementation

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 559-566

  Köster, Markus ^a   Teich, Jürgen ^a  

^a UNIVERSITY OF PADERBORN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMIC SOLUTIONS; FORMAL MODEL; OUTPUT FUNCTIONS; RECONFIGURABLE; RECONFIGURABLE LOGIC; RECONFIGURATION OVERHEAD; STATE MACHINE; TRANSITION FUNCTIONS;

COMPUTER HARDWARE; EXHIBITIONS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; LOGIC DEVICES;

RECONFIGURABLE HARDWARE;

EID: 33846977823     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998356     Document Type: Conference Paper

References (15)

1. K. Bondalapati and V. K. Prasanna. Mapping loops onto reconfigurable architectures. In Int. Workshop on Field- Programmable Logic and Applications (FPL), Sept. 1998.
2. G. Brebner. The swappable logic unit: a paradigm for virtual hardware. In IEEE Symp. on FPGAs and Custom Computing Machines (FCCM), 1997.
3. S. P. Fekete, E. Köhler, and J. Teich. Optimale FPGA module placement with temporal precedence constraints. In Proc. DATE 2001, Design, Automation and Test in Europe, pages 658-665, Munich, Germany, March 13-16 2001. IEEE Computer Society Press.
4. P. C. French and R. W. Taylor. A self-reconfiguring processor. In IEEE Symp. on FPGAs and Custom Computing Machines (FCCM), pages 50-59, Apr. 1993.
5. M. Garey and D. Johnson. Computers and Intractability: A Guide to the Theory of NP-Completeness. Freeman, New York, 1976.
6. R. Hartenstein and H. Grünbacher(Editors). Fieldprogrammable logic and applications : The roadmap to reconfigurable computing. In Proc. 10th Int. Workshop FPL2000, Aug. 2000.
7. M. Köster. Konzept und Implementierung selbstrekonfigurierender Zustandsmaschinen. Master's thesis, Universität-GH Paderborn, Fachbereich Elektrotechnik und Informationstechnik, Fachgebiet Datentechnik, 2001.
8. M. Motomura, Y. Aimoto, A. Shibayama, Y. Yabe, and M. Yamashina. An embedded DRAM-FPGA chip with instantaneous logic reconfiguration. In Symp. on VLSI Circuits Digest of Technical Papers, pages 55-56, June 1997.
9. R. Sidhu, A. Mei, and V. K. Prasanna. Genetic programming using self-reconfigurable FPGAs. In Int.Workshop on Field- Programmable Logic and Applications (FPL), Aug. 1999.
10. R. Sidhu, A. Mei, and V. K. Prasanna. String matching on multicontext FPGAs using self-reconfiguration. In Proc. 7th Int. Symposium on Field Programmable Gate Arrays (FPGA), 1999.
11. J. Teich. Digitale Hardware/Software-Systeme: Synthese und Optimierung. Springer-Lehrbuch, Heidelberg, New York, Tokio, 1997.
12. J. Teich, S. Fekete, and J. Schepers. Optimization of dynamic hardware reconfigurations. The J. of Supercomputing, 19(1):57-75, May 2000.
13. S. Trimberger, D. Carberry, A. Johnson, and J. Wong. A time-multiplexed FPGA. In IEEE Symp. on FPGAs and Custom Computing Machines (FCCM), pages 22-28, Apr. 1997.
14. S. Wadhwa and A. Dandalis. Efficient self-reconfigurable implementations using on-chip memory. In Int.Workshop on Field-Programmable Logic and Applications (FPL), Aug. 2000.
15. Xilinx. XC6200 field programmable gate arrays. Technical report, Xilinx, Inc., October 1996.