An FPGA-based parallel sorting architecture for the Burrows wheeler transform

Proceedings - ReConFig 2005: 2005 International Conference on Reconfigurable Computing and FPGAs

Volumn 2005, Issue , 2005, Pages

  Martínez, José ^a   Cumplido, René ^a   Feregrino, Claudia ^a  

^a INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA COMPRESSION; DATA REDUCTION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

BURROWS WHEELER TRANSFORM; CONTROL UNITS; PARALLEL SORTING;

PARALLEL PROCESSING SYSTEMS;

EID: 33846952832     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RECONFIG.2005.9     Document Type: Conference Paper

References (6)

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2. D. Baron and Y. Bresler, "Antisequential Suffix Sorting For BWT-Base Data Compression", IEEE Transactions on Computers, Vol. 54, No4, April 2005.
3. M. Burrows and D.J. Wheeler, "A Block-Sorting Lossless Data Compression Algorithm," SRC Research Report 124, Digital Systems Research Center, Palo Alto, Calif., May 1994.
4. th International Workshop on Rapid System Prototyping, (RSP'01), IEEE, 2001.
5. M. Effros, "PPM Performance with BWT Complexity: A Fast and Effective Data Compression Algorithm", Proc. IEEE, vol. 88, no. 11, pp. 1703-1712, Nov. 2000.
6. M. Nelson, "Data Compression with the Burrows-Wheeler Transform", Dr. Dobb's Journal, September, 1996.