An exploration of the technology space for multi-core memory/logic chips for highly scalable parallel systems

Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems

Volumn 2005, Issue , 2005, Pages 55-64

  Kogge, Peter M ^a  

^a UNIVERSITY OF NOTRE DAME   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP-LEVEL MULTI-PROCESSING; CHIP-LEVEL SYSTEMS; MEMORY HIERARCHY; MEMORY STRUCTURES;

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DYNAMIC RANDOM ACCESS STORAGE; PARALLEL PROCESSING SYSTEMS; STATIC RANDOM ACCESS STORAGE; STORAGE ALLOCATION (COMPUTER);

INTEGRATED CIRCUITS;

EID: 33846945722     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWIA.2005.24     Document Type: Conference Paper

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