Measurement-based method to characterize parasitic parameters of the integrated power electronics modules

IEEE Transactions on Power Electronics

Volumn 22, Issue 1, 2007, Pages 54-62

  Yang, Liyu ^a   Odendaal, Willem G Hardus ^b  

^a NORTH CAROLINA STATE UNIVERSITY   (United States)

^b State University   (United States)

Author keywords

Characterization; Common mode (CM); Differential mode (DM); Electromagnetic compatibility (EMC); Electromagnetic interference (EMI); Integrated power electronics modules (IPEMs); Measurement; Noise; Packaging; Parasitic capacitance; Parasitic inductors

Indexed keywords

CAPACITANCE; ELECTRIC IMPEDANCE; ELECTRIC IMPEDANCE MEASUREMENT; ELECTRIC INDUCTORS; ELECTROMAGNETIC COMPATIBILITY; ELECTRONICS PACKAGING; MATHEMATICAL MODELS;

INTEGRATED POWER ELECTRONICS MODULES (IPEMS); PARASITIC CAPACITANCE; PARASITIC INDUCTORS;

POWER ELECTRONICS;

EID: 33846919140     PISSN: 08858993     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPEL.2006.886615     Document Type: Article

References (15)

1. J. D. van Wyk and F. C. Lee, "Power electronics technology at the dawn of the new millenium-status and future," in Proc. PESC'99, Charleston, SC, Jun. 27-Jul. 1 1999, vol. 1, pp. 3-12.
2. J. D. van Wyk and F. C. Lee, "Power electronics technology - status and future,"," in Proc. VPEC Sem., Blacksburg, VA, Sep. 19-21, 1999, pp. 61-70.
3. G. Lu and X. Liu, "Application of solderable devices for assembling three-dimensional power electronics modules," in Proc. PESC'00, Galway, Ireland, Jun. 18-23, 2000, vol. 3, pp. 1261-1266.
4. Z. Liang and F. C. Lee, "Embedded power technology for IPEMs packaging applications," in Proc. APEC'01, Anaheim, CA, Mar. 4-8, 2001, vol. 2, pp. 1057-1061.
5. J. Z. Chen, Y. Wu, D. Borojevich, and J. H. Bohn, "Integrated electrical and thermal modeling and analysis of IPEMs," in Proc. COMPEL'00, Blacksburg, VA, Jul. 16-18, 2000, pp. 24-27.
6. W. Teulings, J. L. Schanen, and J. Roudet, "A new technique for spectral analysis of conducted noise of a SMPS including interconnects," in Proc. PESC'97, St. Louis, MO, Jun. 22-27, 1997, vol. 2, pp. 1516-1521.
7. M. Kchikach, Y. S. Yuan, Z. M. Qian, and M. H. Pong, "Modeling and simulation for conducted common-mode current in switching circuits," in Proc. EMC'01 Int. Symp., 2001, vol. 1, pp. 681-685.
8. H. Zhu, A. R. Hefner, and J. Lai, "Characterization of power electronics system interconnect parasitics using time domain reflectometry," in Proc. IEEE PESC'98, Fukuoka, Japan, May 17-22, 1998, vol. 2, pp. 1937-1943.
9. M. T. Zhang, "Electrical, Thermal, and EMI Designs of High-Density, Low-Profile Power Supplies," Ph.D. dissertation, Virginia Polytech. Inst. State Univ., Blacksburg, 1997.
10. M. Trivedi and K. Shenai, "Parasitic extraction methodology for insulated gate bipolar transistors," IEEE Trans. Power Electron., vol. 15, no. 4, pp. 799-804, Jul. 2000.
11. E. McShane and K. Shenai, "RF de-embedding technique for extracting power MOSFET package parasitics," in Proc. Int. Workshop Integr. Power Packag., 2000, pp. 55-59.
12. W. Zhang, M. T. Zhang, F. C. Lee, J. Roudet, and E. Clavel, "Conducted EMI analysis of a boost PFC circuit," in Proc. APEC'97, Atlanta, GA, Feb. 23-27, 1997, vol. 1, pp. 223-229.
13. B. Gutsmann, P. Mourick, and D. Silber, "Exact inductive parasitic extraction for analysis of IGBT parallel switching including DCB-backside eddy currents," in Proc. PESC'00, Galway, Ireland, Jun. 18-23, 2000, vol. 3, pp. 1291-1295.
14. N. Dai and F. C. Lee, "Characterization and analysis of parasitic parameters and their effects in power electronics circuit," in Proc. PESC'96, Baveno, Italy, Jun. 23-27, 1996, vol. 2, pp. 1370-1375.
15. L. Yang, F. C. Lee, and W. G. Odendaal, "Measurement-based characterization method for integrated power electronics modules," in Proc. APEC'03, Miami Beach, FL, Feb. 9-13, vol. 1, pp. 490-496.