HW/SW partitioned optimization and VLSI-FPGA implementation of the MPEG-2 video decoder

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2003, Pages 238-243

  Verderber, Matjaz ^a   Zemva, Andrej ^a   Lampret, Damjan ^b  

^a UNIVERSITY OF LJUBLJANA   (Slovenia)

^b Flextronics Design   (Slovenia)

Author keywords

[No Author keywords available]

Indexed keywords

FLEXTRONICS; FPGA DEVICES; MPEG-2 VIDEO; PARTITIONED SYSTEMS; RISC PROCESSORS; VERILOG; VIDEO DECODERS;

EXHIBITIONS; MOTION PICTURE EXPERTS GROUP STANDARDS; REDUCED INSTRUCTION SET COMPUTING;

OPTIMIZATION;

EID: 33846896417     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2003.1253835     Document Type: Conference Paper

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