Power-manageable scheduling technique for control dominated high-level synthesis

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 1016-1020

  Chen, Chunhong ^a   Sarrafzadeh, Majid ^b  

^a UNIVERSITY OF WINDSOR   (Canada)

^b Engineering IV   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL STEPS; DIGITAL SYSTEM DESIGN; HIGH LEVEL SYNTHESIS; POWER EFFICIENT; POWER OPTIMIZATION; POWER-MANAGEMENT PROBLEM; SCHEDULING TECHNIQUES; TIMING CONSTRAINTS;

DATA FLOW ANALYSIS; DATA FLOW GRAPHS; EXHIBITIONS; OPTIMIZATION; TIMING CIRCUITS;

SCHEDULING;

EID: 33846680049     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998424     Document Type: Conference Paper

References (5)

1. D. D. Gajski and L. Ramachandran, "Introduction to High-Level Synthesis," IEEE Design and Test of Computers, pp.44-54, 1994.
2. A. Chandrakasan, M. Potkonjak, J. Rabaey, and R. Broderson, "HYPER-LP: A System for Power Minimization Using Architectural Transformations," In Proc. of ICCAD, pp.300-303, Nov. 1992.
3. R. Mehra and J. Rabaey, "Behavioral Level Power Estimation and Exploration," IWLPD94, pp.197-202.
4. J. Monteiro, S. Devadas, P. Ashar, and A. Mauskar, "Scheduling Technique to Enable Power Management," In Proc. of DAC, pp.349-352, 1996.
5. C. Chen, X. Yang, and M. Sarrafzadeh, "Potential Slack: An Effective Metric of Combinational Circuit Performance," in Proc. of ICCAD, pp. 198-201, Nov. 2000.