Transient processor/bus fault tolerance for embedded systems: With hybrid redundancy and data fragmentation

IFIP International Federation for Information Processing

Volumn 225, Issue , 2006, Pages 135-144

  Girault, Alain ^a   Kalla, Hamoudi ^b   Sorel, Yves ^c  

^a INRIA RHÔNE ALPES   (France)

^b CAMPUS DE BEAULIEU   (France)

^c INRIA ROCQUENCOURT   (France)

Author keywords

Data fragmentation; Heterogeneous architectures; Hybrid redundancy; Real time embedded systems; Safety critical systems; Scheduling heuristics; Transient faults

Indexed keywords

COMPUTER ARCHITECTURE; FAULT DETECTION; FAULT TOLERANCE; HEURISTIC ALGORITHMS; PARALLEL PROCESSING SYSTEMS; REAL TIME SYSTEMS; REDUNDANCY; SAFETY ENGINEERING; SCHEDULING; SCHEDULING ALGORITHMS; SYSTEMS ANALYSIS;

DATA FRAGMENTATION; HETEROGENEOUS ARCHITECTURES; HYBRID REDUNDANCY; REAL-TIME EMBEDDED SYSTEMS; SAFETY CRITICAL SYSTEMS; SCHEDULING HEURISTICS; TRANSIENT FAULTS;

EMBEDDED SYSTEMS;

EID: 33846679285     PISSN: 15715736     EISSN: None     Source Type: Book Series    
DOI: 10.1007/978-0-387-39362-9_15     Document Type: Conference Paper

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