Experimental and numerical investigation of the reliability of double-sided area array assemblies

Journal of Electronic Packaging

Volumn 128, Issue 4, 2006, Pages 441-448

  Chaparala, S ^a   Pitarresi, J M ^a   Parupalli, S ^a,c   Mandepudi, S ^a   Meilunas, M ^b  

^a State University of New York   (United States)

^b UNIVERSAL INSTRUMENTS CORPORATION   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENDING (DEFORMATION); CHIP SCALE PACKAGES; COMPUTER SIMULATION; CRACK PROPAGATION; FATIGUE OF MATERIALS; FINITE ELEMENT METHOD; FLIP CHIP DEVICES; INTERFEROMETRY; MATHEMATICAL MODELS; MOIRE FRINGES; PRINTED CIRCUIT BOARDS; RELIABILITY; ROUTERS; SOLDERED JOINTS; SURFACE MOUNT TECHNOLOGY; THERMAL CYCLING;

DOUBLE-SIDED AREA ARRAY ASSEMBLIES; PLASTIC BALL GRID ARRAYS (PBGA); THREE-DIMENSIONAL FINITE ELEMENT MODELS;

ARRAYS;

EID: 33846670536     PISSN: 10437398     EISSN: None     Source Type: Journal    
DOI: 10.1115/1.2353280     Document Type: Article

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