From TLM to FPGA: Rapid prototyping with systemC and transaction level modeling

Proceedings - 2005 IEEE International Conference on Field Programmable Technology

Volumn 2005, Issue , 2005, Pages 285-286

  Klingauf, Wolfgang ^a   Günzel, Robert ^a  

^a TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER ARCHITECTURE; COMPUTER HARDWARE; MATHEMATICAL MODELS; NETWORK PROTOCOLS; DISPENSERS; HIGH LEVEL SYNTHESIS; REFINING; SPECIFICATIONS;

COMMUNICATION WRAPPERS; PROTOTYPE GENERATION; TRANSACTION LEVEL MODELS (TLM);

FIELD PROGRAMMABLE GATE ARRAYS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

COMMUNICATIONS CHANNELS; COMMUNICATIONS PROTOCOLS; DESIGN METHODOLOGY; FPGA IMPLEMENTATIONS; MODEL SPECIFICATIONS; PROTOTYPE GENERATIONS; RAPID-PROTOTYPING; SYSTEMC; SYSTEMC LEVEL; TRANSACTION-LEVEL MODEL;

EID: 33846647497     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2005.1568563     Document Type: Conference Paper

References (5)

1. S. Abdi and D. Gajski. Automatic Communication Refinement for System Level Design. Proc. DAC, 2003.
2. W. Klingauf. Systematic Transaction Level Modeling of Embedded Systems with SystemC. Proc. DATE, 2005.
3. W. Klingauf and R. Guenzel. Rapid Prototyping with SystemC and Transaction Level Modeling. Technical Report, Dept. E.I.S., TU Braunschweig, 2005.
4. A. Siebenborn, O. Bringmann, and W. Rosenstiel. Communication Analysis for System on Chip Design. Proc. DATE, 2004.
5. N. Zergainoh, A. Baghdadi, and A. Jerraya. Hardware/Software Codesign of On-chip Communication Architecture for Application-Specific Multiprocessor System-On-Chip. Int. Journal of Embedded Systems, 2004.