Simulation and optimization of solution flow in fountain-plating cup for Au bumping

ICEPT 2003 - 5th International Conference on Electronic Packaging Technology, Proceedings

Volumn , Issue , 2003, Pages 110-114

  Hu, Tao ^a   Wang, Shuidi ^a   Wang, Haining ^a   Cai, Jian ^a   Jia, Songliang ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

Computational fluid dynamics; Consumer products; Electrodes; Flip chip; Glass; Gold; Microelectronics; Packaging; Resists; Wafer bonding

Indexed keywords

CONSUMER PRODUCTS; ELECTRODES; ELECTRONICS PACKAGING; FLUID DYNAMICS; FOUNTAINS; GLASS; GLASS BONDING; GOLD; MICROELECTRONICS; PACKAGING; WAFER BONDING;

6 INCH WAFERS; AU BUMP; FLIP CHIP; HOLE SIZE; RESISTS; SIMULATION AND OPTIMIZATION; SOLUTION FLOWS; TSINGHUA UNIVERSITY;

COMPUTATIONAL FLUID DYNAMICS;

EID: 33846329183     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2003.1298703     Document Type: Conference Paper

References (5)

1. L. Dietrich, J. Wolf, et al, (1998), Wafer bumping technique using electroplating for high-dense chip packaging. Proceedings of the Third International Symposium on Electronic Packaging Technology, Beijing: Tsinghua University Press, pp:405-412.
2. Shuidi Wang, Jianghua Guo, (2001), Rapidly developed wafer level packaging, 21 century devices, No. 10, pp: 39-41.
3. Tao Hu, Zhimin Tan, Zhonghui Zhang, Songliang Jia, (2001) Design and fabricating of Au bumps for Flip Chip, Semiconductor Industry, No. 2 pp:32-34
4. Rui'an Zhu, Zhenchang Guo, (1987) Pulse Plating, Electronics Industry Press, China
5. Tien-Yu, Tom Lee, et al. (1996), Application of a CFD Tool in Designing a Fountain Plating Cup for Uniform Bump Plating of Semiconductor Wafers. IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part B, Vol.19, No.1, pp:131-137