A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 2389-2392

  Tongprasit, Benjamas ^a   Ito, Kiyoto ^a   Shibata, Tadashi ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT-SERIAL; FILTERING OPERATIONS; PROCESSING UNITS; RANK-ORDER FILTERING;

DYNAMIC POSITIONING; IMAGE PROCESSING; PIXELS; READOUT SYSTEMS; SENSORS; SIGNAL FILTERING AND PREDICTION; SIGNAL PROCESSING; VLSI CIRCUITS;

DIGITAL CIRCUITS;

EID: 33846264897     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465106     Document Type: Conference Paper

References (4)

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2. B. K. Kar, D. K. Pradhan, "A new algorithm for order statistic and sorting," IEEE Trans. Signal Processing, vol. 41, no. 8, pp. 2688-2694.
3. S. Kleinfelder, S. Lim, X. Liu, and A. El Gamal, "A 10000 frames/s CMOS digital pixel sensor," IEEE J. Solid-State Circuits, vol. 36, pp. 2049-2059, December 2001.
4. K. Ito, M. Ogawa, T. Shibata, "A Variable-Kernel Flash-Convolution Image Filtering Processor," IEEE Int. Solid-State Circuits Conf., Paper No. 26. 7, pp. 470-471, February 2003.