Multi-mode operator for SHA-2 hash functions

Journal of Systems Architecture

Volumn 53, Issue 2-3, 2007, Pages 127-138

  Glabb, Ryan ^a   Imbert, Laurent ^a,b,c   Jullien, Graham ^a   Tisserand, Arnaud ^b   Veyrat Charvillon, Nicolas ^d  

^a UNIVERSITY OF CALGARY   (Canada)

^b LIRMM   (France)

^c UNIVERSITY OF CALGARY   (Canada)

^d UNIVERSITÉ DE LYON   (France)

Author keywords

FPGA; Hash function; Multi mode operator; SHA 2 family

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; FUNCTIONS; SERVERS;

FREQUENCY VERSION; HASH FUNCTION; MINIMAL OPERATOR LATENCY; MULTI-MODE OPERATOR; SHA-2 HASH FAMILY;

MATHEMATICAL OPERATORS;

EID: 33846253665     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2006.09.006     Document Type: Article

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