65nm CMOS technology for low power applications

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 64-67

  Steegen, A ^a   Mo, R ^a   Mann, R ^a   Sun, M C ^d   Eller, M ^c   Leake, G ^a   Vietzke, D ^c   Tilke, A ^c   Guarin, F ^a   Fischer, A ^c   Pompl, T ^c   Massey, G ^a   Vayshenker, A ^a   Tan, W L ^b   Ebert, A ^a   Lin, W ^b   Gao, W ^b   Lian, J ^c   Kim, J P ^d   Wrschka, P ^a   Yang, J H ^d   Ajmera, A ^a   Knoefler, R ^c   Teh, Y W ^b   Jamin, F ^a   Park, J E ^d   Hooper, K ^a   Griffin, C ^a   Nguyen, P ^a   Klee, V ^c   Ku, V ^a   Baiocco, C ^a   Johnson, G ^a   Tai, L ^a   Benedict, J ^a   Scheer, S ^a   Zhuang, H ^c   Ramanchandran, V ^a   Matusiewicz, G ^a   Lin, Y H ^a   Siew, Y K ^b   Zhang, F ^b   Leong, L S ^b   Liew, S L ^b   Park, K C ^d   Lee, K W ^d   Hong, D H ^d   Choi, S M ^d   Kaltalioglu, E ^c   Kim, S O ^c   Naujok, M ^c   Sherony, M ^a   Cowley, A ^a   Thomas, A ^a   Sudijohno, J ^b   Schiml, T ^c   Ku, J H ^d   Yang, I ^a   more..

^a IBM RESEARCH   (United States)

^b Chartered Semiconductor Manufacturing ^*  (Singapore)

^c INFINEON TECHNOLOGIES AG   (Germany)

^d SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

DRIVE CURRENTS; DUAL GATE OXIDES; HALO IMPLANTS;

COMPUTATIONAL COMPLEXITY; COPPER; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; GATE DIELECTRICS; HIERARCHICAL SYSTEMS;

CMOS INTEGRATED CIRCUITS;

EID: 33846007503     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Z. Luo et al., IEDM 2004, pp.661.
2. A. Chatterjee et al., IEDM 2004, pp.665.
3. B. Duriez et al., IEDM 2004, pp.847.