-
2
-
-
0025404493
-
Executing a program on the MIT tagged-token dataflow architecture
-
K. Arvind and R. S. Nikhil. Executing a Program on the MIT Tagged-Token Dataflow Architecture. IEEE Trans. Comput., vol. 39, pp. 300-18, 1990.
-
(1990)
IEEE Trans. Comput.
, vol.39
, pp. 300-318
-
-
Arvind, K.1
Nikhil, R.S.2
-
5
-
-
0014814325
-
Space/time trade-offs in hash coding with allowable errors
-
B. H. Bloom. Space/Time Trade-Offs in Hash Coding with Allowable Errors. Commun. ACM, vol. 13, pp. 422-6, 1970.
-
(1970)
Commun. ACM
, vol.13
, pp. 422-426
-
-
Bloom, B.H.1
-
9
-
-
0033689702
-
Architectural support for scalable speculative parallelization in shared-memory multiprocessors
-
M. Cintra, J. Martinez, et al., "Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors," In Proc. of the 27th Annual Intl. Symp. on Comp. Arch., pp. 13-24, 2000.
-
(2000)
Proc. of the 27th Annual Intl. Symp. on Comp. Arch.
, pp. 13-24
-
-
Cintra, M.1
Martinez, J.2
-
11
-
-
0017907315
-
The architecture and system method of DDM1: A recursively structured data driven machine
-
A. L. Davis, "The Architecture and System Method of DDM1: A Recursively Structured Data Driven Machine," In Proc. Of the 5th Annual Symp. On Comp. Arch., pp. 210-5, 1978.
-
(1978)
Proc. of the 5th Annual Symp. on Comp. Arch.
, pp. 210-215
-
-
Davis, A.L.1
-
12
-
-
0016434955
-
A preliminary architecture for a basic data-flow processor
-
J. B. Dennis, "A Preliminary Architecture for a Basic Data-Flow Processor," In Proc. Of the 2nd Intl. Symp. On Comp. Arch., pp. 125-31, 1975.
-
(1975)
Proc. of the 2nd Intl. Symp. on Comp. Arch.
, pp. 125-131
-
-
Dennis, J.B.1
-
14
-
-
0032308864
-
Dataflow analysis of branch mispredictions and its application to early resolution of branch outcomes
-
A. Farcy, O. Temam, et al., "Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes," In Proc. Of the 31st Annual Intl. Symp. On Microarch., pp. 59-68, 1998.
-
(1998)
Proc. of the 31st Annual Intl. Symp. on Microarch.
, pp. 59-68
-
-
Farcy, A.1
Temam, O.2
-
15
-
-
84976724394
-
Implementing functional programs on a hypercube multiprocessor
-
B. Goldberg and P. Hudak, "Implementing Functional Programs on a Hypercube Multiprocessor," In Proc. Of the Third Conf. On Hypercube Concurrent Computers and Applications: Architecture, Software, Computer Systems, and General Issues, pp. 489-504, 1988.
-
(1988)
Proc. of the Third Conf. on Hypercube Concurrent Computers and Applications: Architecture, Software, Computer Systems, and General Issues
, pp. 489-504
-
-
Goldberg, B.1
Hudak, P.2
-
20
-
-
0017504498
-
Viewing control structures as patterns on passing messages
-
C. Hewitt. Viewing Control Structures as Patterns on Passing Messages. Journal of Artificial Intelligence, vol. 8, pp. 323-64, 1977.
-
(1977)
Journal of Artificial Intelligence
, vol.8
, pp. 323-364
-
-
Hewitt, C.1
-
24
-
-
0034839064
-
Tolerating memory latency through software-controlled pre-execution in simultaneous multithreading processors
-
C.-K. Luk, "Tolerating Memory Latency through Software-Controlled Pre-Execution in Simultaneous Multithreading Processors," In Proc. Of the 28th Annual Intl. Symp. On Comp. Arch., pp. 40-51, 2001.
-
(2001)
Proc. of the 28th Annual Intl. Symp. on Comp. Arch.
, pp. 40-51
-
-
Luk, C.-K.1
-
31
-
-
0038346243
-
Reenact: Using thread-level speculation mechanisms to detect data races in multithreaded code
-
M. Prvulovic and J. Torellas, "Reenact: Using Thread-Level Speculation Mechanisms to Detect Data Races in Multithreaded Code," In Proc. of the 30th Annual Intl. Symp. on Comp. Arch., pp. 110-21, 2003.
-
(2003)
Proc. of the 30th Annual Intl. Symp. on Comp. Arch.
, pp. 110-121
-
-
Prvulovic, M.1
Torellas, J.2
-
33
-
-
32844465384
-
Tasking with out-of-order spawn in Tls chip multiprocessors: Microarchitecture and compilation
-
J. Renau, J. Tuck, et al., "Tasking with out-of-Order Spawn in Tls Chip Multiprocessors: Microarchitecture and Compilation," In Proceedings of the 19th annual Intl. Conf. on Supercomputing, pp. 179-88, 2005.
-
(2005)
Proceedings of the 19th Annual Intl. Conf. on Supercomputing
, pp. 179-188
-
-
Renau, J.1
Tuck, J.2
-
39
-
-
0035311433
-
Speculative multithreaded processors
-
G. S. Sohi and A. Roth. Speculative Multithreaded Processors. Computer, vol. 34, pp. 66-73, 2001.
-
(2001)
Computer
, vol.34
, pp. 66-73
-
-
Sohi, G.S.1
Roth, A.2
-
40
-
-
0031605348
-
The potential for using thread-level data speculation to facilitate automatic parallelization
-
J. Steffan and T. Mowry, "The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization," In Proc. of the 4th Intl. Symp. on High-Perf. Comp. Arch., pp. 1-12, 1998.
-
(1998)
Proc. of the 4th Intl. Symp. on High-perf. Comp. Arch.
, pp. 1-12
-
-
Steffan, J.1
Mowry, T.2
-
43
-
-
0033344478
-
The superthreaded processor architecture
-
J.-Y. Tsai, J. Huang, et al. The Superthreaded Processor Architecture. IEEE Transactions on Computers, vol. 48, pp. 881-902, 1999.
-
(1999)
IEEE Transactions on Computers
, vol.48
, pp. 881-902
-
-
Tsai, J.-Y.1
Huang, J.2
-
46
-
-
21644447484
-
Accmon: Automatically detecting memory-related bugs via program counter-based invariants
-
P. Zhou, W. Liu, et al., "Accmon: Automatically Detecting Memory-Related Bugs Via Program Counter-Based Invariants," In Proc. of the 37th Annual Intl. Symp. on Microarch., pp. 260-80, 2004.
-
(2004)
Proc. of the 37th Annual Intl. Symp. on Microarch.
, pp. 260-280
-
-
Zhou, P.1
Liu, W.2
-
48
-
-
33845899186
-
Time-shifted modules: Exploiting code modularity for fine grain parallelism
-
University of Wisconsin-Madison
-
C. B. Zilles and G. S. Sohi, "Time-Shifted Modules: Exploiting Code Modularity for Fine Grain Parallelism," University of Wisconsin-Madison, Computer Sciences Dopt. TR1430, 2001.
-
(2001)
Computer Sciences Dopt. TR1430
-
-
Zilles, C.B.1
Sohi, G.S.2
|