Multirate simulations with simultaneous-solution using direct integration methods in a partitioned network environment

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 53, Issue 12, 2006, Pages 2765-2778

  Moreira, Fernando A ^a   Martí, José R ^b   Zanetta Jr , Luiz C ^c   Linares, Luis R ^b  

^a FEDERAL UNIVERSITY OF BAHIA   (Brazil)

^b UNIVERSITY OF BRITISH COLUMBIA   (Canada)

^c UNIVERSITY OF SÃO PAULO   (Brazil)

Author keywords

Circuit latency exploitation; Multi area Thevenin equivalents (MATEs); Multirate simulation; Numerical integration rules

Indexed keywords

COMPUTER SIMULATION; INTEGRATION; ITERATIVE METHODS;

CIRCUIT LATENCY; CIRCUIT LATENCY EXPLOITATION; MULTI-AREA THEVENIN EQUIVALENTS (MATES); MULTIRATE SIMULATION;

EQUIVALENT CIRCUITS;

EID: 33845748258     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2006.882821     Document Type: Article

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