A 1.9-GHz single-chip CMOS PHS cellphone

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 12, 2006, Pages 2737-2743

  Si, William W ^a,b   Mehta, Srenik ^a,b   Samavati, Hirad ^a,b   Terrovitis, Manolis ^a,b   Mack, Michael ^a,b   Onodera, Keith ^a,b   Jen, Steve ^a,b   Luschas, Susan ^a,b   Hwang, Justin ^a,b   Mendis, Suni ^a,b   Su, David ^a,b   Wooley, Bruce ^a,c  

^a IEEE   (United States)

^b Atheros Communications   (United States)

^c STANFORD UNIVERSITY   (United States)

Author keywords

CMOS integrated circuits; Direct conversion; Fast settling synthesizer; Fractional N synthesizer; Frequency synthesizer; Personal handy phone (PHS); Phase noise; Phase locked loop (PLL); RF transceiver; Transceiver

Indexed keywords

DIRECT CONVERSION; FAST SETTLING SYNTHESIZER; FRACTIONAL-N SYNTHESIZER; PERSONAL HANDY PHONE (PHS); PHASE NOISE; RF TRANSCEIVER;

ANALOG TO DIGITAL CONVERSION; CELLULAR TELEPHONE SYSTEMS; FREQUENCY SYNTHESIZERS; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; MODEMS; PHASE LOCKED LOOPS; TIME DIVISION MULTIPLE ACCESS; TRANSCEIVERS;

CMOS INTEGRATED CIRCUITS;

EID: 33845615812     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.884790     Document Type: Conference Paper

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