Wire bond, flip-chip and chip-scale-package solution to high silicon integration

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 1386-1391

  Bantog, Ely ^a   Chiu, Steve ^a   Chen, C T ^a   Pu, H P ^a   Hsiao, C S ^a  

^a SILICONWARE PRECISION INDUSTRIES CO LTD   (Taiwan)

Author keywords

Delamination; EMC; Flip chip; Mold + underfill; Reliability; Stacked die; UF; Wire bond

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; DELAMINATION; DYNAMIC RANDOM ACCESS STORAGE; FLIP CHIP DEVICES; RELIABILITY THEORY; SEMICONDUCTING SILICON; STATIC RANDOM ACCESS STORAGE;

LOGIC FUNCTIONS; STACKED DIES; SYSTEM IN A CHIP (SIP) PACKAGES; WIRE BONDS;

CHIP SCALE PACKAGES;

EID: 33845595303     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645838     Document Type: Conference Paper

References (7)

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