Instruction-based self-testing of delay faults in pipelined processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 14, Issue 11, 2006, Pages 1203-1214

  Singh, Virendra ^a,b   Inoue, Michiko ^a,c   Saluja, Kewal K ^d   Fujiwara, Hideo ^a,c  

^a IEEE   (India)

^b CENTRAL ELECTRONICS ENGINEERING RESEARCH INSTITUTE   (India)

^c NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^d University of Wisconsin Madison   (United States)

Author keywords

At speed test; Delay fault test; Instruction based self test; Microprocessor test

Indexed keywords

AT SPEED TEST; DELAY FAULT TEST; INSTRUCTION BASED SELF TEST; MICROPROCESSOR TEST;

ELECTRIC FAULT LOCATION; ELECTRONIC EQUIPMENT TESTING; MATHEMATICAL MODELS; PROGRAM PROCESSORS; VECTORS;

DELAY CIRCUITS;

EID: 33845527218     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2006.886412     Document Type: Article

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