A CMOS tunable transimpedance amplifier

IEEE Microwave and Wireless Components Letters

Volumn 16, Issue 12, 2006, Pages 693-695

  Hwang, Huei Yan ^b   Chien, Jun Chau ^a,b   Chen, Tai Yuan ^b   Lu, Liang Hung ^a,b  

^a IEEE   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Bit error rate (BER); Input sensitivity; Intersymbol interference (ISI); Optical receiver; Regulated cascode; Total integrated noise; Transimpedance amplifier (TIA); Tunable bandwidth

Indexed keywords

OPTICAL RECEIVERS; TOTAL INTEGRATED NOISE; TRANSIMPEDANCE AMPLIFIER (TIA); TUNABLE BANDWIDTH;

BANDWIDTH; BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; ELECTRIC IMPEDANCE; GAIN CONTROL; INTERSYMBOL INTERFERENCE;

POWER AMPLIFIERS;

EID: 33845521027     PISSN: 15311309     EISSN: None     Source Type: Journal    
DOI: 10.1109/LMWC.2006.885641     Document Type: Article

References (6)

1. H. Shigematsu, M. Sato, T. Suzuki, T. Tkkahashi, K. Imanishi, N. Hara, H. Ohnishi, and Y. Watanabe, "A 49-GHz preamplifier with a transimpedance gain of 52 dBΩ using InP HEMTs," IEEE J. Solid-State Circuits, vol. 36, no. 9, pp. 1309-1313, Sep. 2001.
2. C. Q. Wu, E. A. Sovero, and B. Massey, "40-GHz trans- impedance amplifier with differential outputs using InP-InGaAs heterojunction bipolar transistors," IEEE J. Solid-State Circuits, vol. 38, no. 9, pp. 1518-1523, Sep. 2003.
3. S. M. Park and H.-J. Yoo, "1.25-Gb/s regulated cascode CMOS transimpedance amplifier for gigabit Ethernet applications," IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 112-121, Jan. 2004.
4. W.-Z. Chen and R.-M. Can, "1.8 V, variable gain transimped- ance amplifier with constant damping factor for burst-mode optical receiver," in IEEE RFIC Symp. Dig., Jun. 2005, pp. 12-14.
5. C. Kromer, G. Sialm, T. Morf, M. L. Schmatz, F. Ellinger, D. Erni, and H. Jackel, "A low-power 20-GHz 52- dBΩ transimped- ance amplifier in 80-nm CMOS," IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 885-894, Jun. 2004.
6. C.-H. Wu, C.-H. Lee, W.-S. Chen, and S.-I. Liu, "CMOS wide- band amplifiers using multiple inductive-series peaking tech- nique," IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 548-552, Feb. 2005.