Two-level logic synthesis on PAL-based CPLD and FPGA using decomposition

Conference Proceedings of the EUROMICRO

Volumn 1, Issue , 1999, Pages 278-281

  Kania, Dariusz ^a  

^a SILESIAN UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUIT; FPGA DEVICES; INTERNAL RESOURCES; LOGIC BLOCKS; LOGIC SYNTHESIS; OUTPUT BUFFER; SYNTHESIS PROCESS;

MICROWAVE CIRCUITS;

INFORMATION SCIENCE;

EID: 33845299965     PISSN: 10896503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.1999.794480     Document Type: Conference Paper

References (12)

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4. S.D. Brown, R.J. Francis, J. Rose, Z.G. Vranesic, Field Programmable GateArrays, Kluwer, 1993, p.45-86
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10. G. Saucier, P. Sicard, G. Bouchet, Multi-level synthesis on PAL's, Proc. EDAC, Glasgow, March 1990, pp.542-546
11. T. Sasao, FPGA Design by Generalized Functional Decomposition in Logic Synthesis and Optimization, Kluwer,1993
12. W. Wan, M.A. Perkowski, A new Approach to the Decomposition of Incompletely Specified Multi-Output Functions Based on Graph Coloring and Local Transformations and Its Applications to FPGA Mapping, Proc. EDAC'92, Brussels