Low-power high-frequency CMOS peak detector

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors

Volumn 27, Issue 10, 2006, Pages 1707-1710

  Li, Xuechu ^a   Gao, Qingyun ^a   Qin, Shicai ^a  

^a NANKAI UNIVERSITY   (China)

Author keywords

CMOS; High frequency; Lower power; Peak detector

Indexed keywords

BANDWIDTH; CALCULATIONS; SIMULATION;

CMOS TECHNOLOGY; CURRENT DISSIPATION; LOW POWER HIGH FREQUENCY CMOS; PEAK DETECTOR; POST SIMULATIONS; THEORETICAL CALCULATIONS;

DETECTORS;

EID: 33751576297     PISSN: 02534177     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (6)

1. Khoury J M. On the design of constant settling time AGC circuits. IEEE Trans Circuits and System-II: Analog and Digital Signal Processing, 1998, 45(3): 283
2. Lee T H. The design of CMOS radio-frequency integrated circuits second edition. Cambridge University Press, 2004: 630
3. Cripps S C. Advanced techniques in RF power amplifier design. Artech House, 2002: 111
4. Meyer R G. Low-power monolithic RF peak detector analysis. IEEE J Solid-State Circuits, 1995, 30(1): 65
5. Godfrey M D. CMOS device modeling for subthreshold circuits. IEEE Trans Circuits and Systems, 1992, 39(8): 532
6. Chen M J, Ho J S. A three-parameters-only MOSFET subthreshold current CAD model considering back-gate bias and process variation. IEEE Trans Computer-Aided Design, 1997, 16: 343