A high efficiency full-chip thermal simulation algorithm

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn 2005, Issue , 2005, Pages 635-638

  Zhan, Yong ^a   Sapatnekar, Sachin S ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FREQUENCY DOMAIN ANALYSIS; GREEN'S FUNCTION; MICROPROCESSOR CHIPS; NANOSTRUCTURED MATERIALS; THERMAL EFFECTS;

DISCRETE COSINE TRANSFORM; MAGNITUDE SPEEDUP; THERMAL SIMULATION;

ALGORITHMS;

EID: 33751427407     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560144     Document Type: Conference Paper

References (13)

1. C. H. Tsai and S. M. Kang, "Cell-Level Placement for Improving Substrate Thermal Distribution," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 2, pp. 253-266, Feb. 2000.
2. B. Goplen and S. S. Sapatnekar, "Efficient Thermal Placement of Standard Cells in 3D ICs Using a Force Directed Approach," Digest of Technical Papers, IEEE/ACM International Conference on Computer-Aided Design, pp. 86-89, Nov. 2003.
3. T. Y. Wang and C. P. Chen, "3-D Thermal-ADI: A Linear-Time Chip Level Transient Thermal Simulator," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 12, pp. 1434-1445, Dec. 2002.
4. Y. K. Cheng and S. M. Kang, "An Efficient Method for Hot-Spot Identification in ULSI Circuits," Digest of Technical Papers, IEEE/ACM International Conference of Computer-Aided Design, pp. 124-127, Nov. 1999.
5. B. Wang and P. Mazumder, "Fast Thermal Analysis for VLSI Circuits via Semi-analytical Green's Function in Multi-layer Materials," IEEE International Symposium on Circuits and Systems, pp. 409-412, May 2004.
6. Y. Zhan and S. S. Sapatnekar, "Fast Computation of the Temperature Distribution in VLSI Chips Using the Discrete Cosine Transform and Table Look-up," Proceedings of the 2005 Asia and South Pacific Design Automation Conference, pp. 87-92, Jan. 2005.
7. P. Li, L. T. Pileggi, M. Asheghi, and R. Chandra, "Efficient Full-Chip Thermal Modeling and Analysis," Digest of Technical Papers, IEEE/ACM International Conference of Computer-Aided Design, pp. 319-326, Nov. 2004.
8. J. P. Costa, M. Chou, and L. M. Silveira, "Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 5, pp. 597-607, May 1999.
9. M. N. Ozisik, "Boundary Value Problems of Heat Conduction," Oxford University Press, Oxford, UK, 1968.
10. A. G. Kokkas, "Thermal Analysis of Multi-Layer Structures," IEEE Transactions on Electron Devices, vol. 21, no. 11, pp. 674-681, Nov. 1974.
11. Y. K. Cheng, P. Raha, C. C. Teng, E. Rosenbaum, and S. M. Kang, "ILLIADS-T: An Electrothermal Timing Simulator for Temperature-Sensitive Reliability Diagnosis of CMOS VLSI Chips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 8, pp. 668-681, Aug. 1998.
12. R. Gharpurey, "Modeling and Analysis of Substrate Coupling in Integrated Circuits," Ph. D. Thesis, UC Berkeley, CA, 1995.
13. A. V. Oppenheim, R. W. Schafer, and J. R. Buck, " Discrete-Time Signal Processing," Prentice Hall, Upper Saddle River, NJ, 1999.