Negative-gate to substrate erase transient simulation for flash memory

Microelectronic Engineering

Volumn 84, Issue 1, 2007, Pages 101-104

  Wolfson, S ^a   Ho, Fat D ^b  

^a Redstone Technical Test Center   (United States)

^b UNIVERSITY OF ALABAMA IN HUNTSVILLE   (United States)

Author keywords

Flash memory; Hot carriers; MOS memory circuits; Semiconductor device models; Simulation

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POTENTIAL; GATES (TRANSISTOR); HOT CARRIERS; POISSON EQUATION; SEMICONDUCTOR DEVICE MODELS; TRANSIENTS;

MOS MEMORY CIRCUITS; SUBSTRATE ERASING; TRANSIENT SIMULATION;

FLASH MEMORY;

EID: 33751420208     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2006.08.008     Document Type: Article

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