LOGO overcome combinational Logic Limitations

Canadian Conference on Electrical and Computer Engineering

Volumn 2005, Issue , 2005, Pages 1061-1064

  Haidar, Ali Massoud ^a   Hoda, Abdullah S Abul ^a   Hamad, Mostapha ^b   Shirahama, Hiroyuki ^c  

^a BEIRUT ARAB UNIVERSITY   (Lebanon)

^b NOTRE DAME UNIVERSITY   (Lebanon)

^c EHIME UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FORMAL LOGIC; HEAT LOSSES; LOGIC PROGRAMMING; NEURAL NETWORKS; TRANSISTORS; ULSI CIRCUITS;

INTERCHIP CONNECTIONS; MULTI-VALUED LOGIC CIRCUITS; REED MULLER ALGEBRA;

COMBINATORIAL MATHEMATICS;

EID: 33751335283     PISSN: 08407789     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CCECE.2005.1557159     Document Type: Conference Paper

References (6)

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2. Haidar, A. M. "A Novel Intelligent Neural Networks for Error Correction Codes". 2000 International Symposium on Nonlinear Theory and its Applications (NOLTA2000), 2000
3. Roth, C. H. Fundamentals of Logic Design. PWS Publishing Company, 1999
4. Nagata, Y. and Mukaidono, M. A Fault Model for MV PLA's and its Equivalence. IEICE Trans. On Fund., Vol EE77-A, No. 9, pp. 1527-1534, Sep. 1994
5. Fausett, F. Fundamentals of Neural Networks Architectures, Algorithms, and Applications. Prentice Hall., 1994
6. Swingler, K. Applying Neural Networks. Academic Press, 1996