Design of randomized multichannel packet storage for high performance routers

Proceedings - Symposium on the High Performance Interconnects, Hot Interconnects

Volumn 2005, Issue , 2005, Pages 100-106

  Kumar, Sailesh ^a   Crowley, Patrick ^a   Turner, Jonathan ^a  

^a UNIVERSITY OF WASHINGTON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH PERFORMANCE ROUTERS; MEMORY BANDWIDTH; MULTICHANNEL PACKET STORAGE; RANDOMIZED PACKET STORAGE;

BANDWIDTH; BUFFER STORAGE; CARRIER COMMUNICATION; COMMUNICATION CHANNELS (INFORMATION THEORY); PACKET NETWORKS; ROUTERS;

RANDOM ACCESS STORAGE;

EID: 33751172530     PISSN: 15504794     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CONECT.2005.17     Document Type: Conference Paper

References (7)

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3. Iyer, S., R. R. Compella, and N. McKeown, "Designing Buffers for Router Line Cards," Stanford University HPNG Technical Report - TR02-HPNG-031001, 2002.
4. Iyer, S., R. R. Kompella, and N. McKeown, "Analysis of a Memory Architecture for Fast Packet Buffers," IEEE HPSR, 5/02.
5. G. Shrimali, I. Keslassy, and N. McKeown, "Designing Packet Buffers with Statistical Guarantees," Hot-Interconnects, Stanford, 8/04.
6. DDR-DRAM, RLDRAM, Micron Technology, Inc.
7. FCRAM, Toshiba America Electronic Components, Inc.