SCT: An approach for testing and configuring nanoscale devices

Proceedings of the IEEE VLSI Test Symposium

Volumn 2006, Issue , 2006, Pages 370-375

  Rad, Reza M P ^a   Tehranipoor, Mohammad ^a  

^a UNIVERSITY OF MARYLAND BALTIMORE COUNTY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECT TOLERANCE; NANOSCALE DEVICES; RECONFIGURABLE NANOBLOCKS; SIMULTANEOUS CONFIGURATION AND TEST (SCT);

BUILT-IN SELF TEST; ELECTRONIC EQUIPMENT; ERROR DETECTION;

NANOTECHNOLOGY;

EID: 33751109027     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2006.61     Document Type: Conference Paper

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