Extending endurance of NROM memories to over 10 million program/erase cycles

21st IEEE Non-Volatile Semiconductor Memory Workshop 2006, NVSMW 2006

Volumn 2006, Issue , 2006, Pages 74-75

  Roizin, Yakov ^a   Pikhay, Evgeny ^a   Lisiansky, Michael ^a   Heiman, Alexey ^a   Alon, Eli ^a   Aloni, Efraim ^a   Fenigstein, Amos ^a  

^a TOWER SEMICONDUCTOR LTD   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC POTENTIAL; ELECTRON TRAPS; OPTIMIZATION; TRANSISTORS;

BOTTOM OXIDE (BOX); CYCLING ALGORITHM; ENHANCED ENDURANCE; PARASITIC ELECTRON TRAPPING;

ROM;

EID: 33751038074     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2006.1629501     Document Type: Conference Paper

References (4)

1. Boaz Eitan, US Patent No 5.768.192, 1998.
2. Efraim Aloni, et. al., SSDM 2000, p.298.
3. Yakov Roizin et al., IEEE NVSMW 2004, p.85.
4. Yen-Hao Shih, et. al., IEDM 2004 p.881.