EMI modeling and simulation in the IC design process

17th International Zurich Symposium on Electromagnetic Compatibility, 2006

Volumn 2006, Issue , 2006, Pages 594-597

  Steinecke, Thomas ^a   Hesidenz, Dirk ^a   Miersch, Ekkehard ^b  

^a INFINEON TECHNOLOGIES AG   (Germany)

^b EFM Consulting   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; ELECTROMAGNETIC WAVES; MICROCONTROLLERS; POWER INTEGRATED CIRCUITS; SIGNAL INTERFERENCE;

DESIGN PHASE; ELECTROMAGNETIC EMISSION; POWER INTEGRITY; SYSTEM CHIP;

INTEGRATED CIRCUIT LAYOUT;

EID: 33751033869     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/emczur.2006.215004     Document Type: Conference Paper

References (6)

1. IBIS Home Page, http://www.eigroup.org/IBIS/Default.htm
2. ICEM Cookbook, ICEM Standard proposal TEC 62014-3.
3. A. Gstoettner, T. Steinecke, M. Huemer, High Level Modeling of Dynamic Switching Currents in VLSI IC Modules, EMC Compo 2005, Munich.
4. A. Gstoettner, T. Steinecke, M. Huemer, Activity Based High Level Modeling of Dynamic Switching Currents in Digital IC Modules, EMC Zurich 2006, Singapore.
5. J. Kane, J. Fang, On-Chip Power Integrity including Package Effects, SOCcentral Publications, March 11, 2005, www.soccentral.com/results.asp?EntryID- 12237.
6. E. Miersch, Signal and Power Integrity Analysis of large complex PCBs : Theory, Implementation, Simulation and Result Verification by Measurements, PIERS 2004, p. 164